
25AA040A/25LC040A
2.7
Data Protection
2.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
? The write enable latch is reset on power-up
? A write enable instruction must be issued to set
the write enable latch
? After a byte write, page write or STATUS register
write, the write enable latch is reset
? CS must be set high after the proper number of
clock cycles to start an internal write cycle
? Access to the array during an internal write cycle
is ignored and programming is continued
The 25XX040A powers on in the following state:
? The device is in low-power Standby mode
(CS = 1 )
? The write enable latch is reset
? SO is in high-impedance state
? A high-to-low-level transition on CS is required to
enter active state
TABLE 2-4:
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
0 (low)
1 (high)
1 (high)
WEL
(SR bit 1)
x
0
1
Protected Blocks
Protected
Protected
Protected
Unprotected Blocks
Protected
Protected
Writable
STATUS Register
Protected
Protected
Writable
x = don’t care
DS21827G-page 12
? 2003-2011 Microchip Technology Inc.